A SFQ-to-CMOS Interface Circuit Based on SiGe BiCMOS for Josephson-CMOS Hybrid System

Abstract

In this article, a novel DC-biased interface for multi-channel superconducting computers was designed, fabricated, and tested. Conventional interfaces for Josephson-CMOS memory rely on Josephson latching drivers (JLDs) or SQUID (Superconducting Quantum Interference Device) stacks to convert weak signals. However, SQUID stacks achieve high frequencies (tens of GHz) but produce only a few millivolts of output and occupy large areas, while JLDs provide higher output voltages (tens of millivolts) but require AC bias. To address these limitations, an interface based on SiGe BiCMOS (Silicon-Germanium Bipolar CMOS) technology was proposed, integrating the functions of JLDs and CMOS amplifiers into a single chip. Fabricated using a 130 nm SiGe BiCMOS process, the interface converts 200 µV to 1.2 V with a power consumption of only 386 µW per channel at 4.2 K. Low-frequency measurements demonstrated 21-channel signal conversion without the need for clock synchronization or additional amplifiers, significantly simplifying the cryogenic system. The proposed interface features key advantages, including DC bias, high gain, and asynchronous operation, making it a practical solution for superconductor–semiconductor signal conversion. While its maximum speed is currently limited, this interface represents a promising step toward scalable, energy-efficient multi-channel superconducting computers.