A novel FD-IGBT with double self-biased floating Schottky diode

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Ao Wu , Haifeng Qin , Zubing Duan , Wei Li , Li Wan , Xiandong Ma , Qiansheng Rao , Weizhong Chen
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引用次数: 0

Abstract

This paper proposes a novel Floating Dummy IGBT (FD-IGBT) featuring integrated N- and P-type Schottky Barrier Diodes (SBDs) and investigates its performance through simulation. During the turn-on transient, hole accumulation in the floating P-base region elevates its quasi-Fermi potential, triggering the turn-on of the two series-connected SBDs and thereby clamping the voltage of the floating P-base region. This mechanism effectively reduces the Miller capacitance and significantly suppresses the reverse gate charging current from the floating P-base region to the gate. This reduces turn-on energy loss (EON) and improves dICE/dt controllability. Under short-circuit conditions, the SBDs adaptively turn on, enhancing short-circuit tolerance time (TSC). During turn-off state, the SBDs accelerate hole extraction, reducing turn-off time and energy loss (EOFF). TCAD simulations show that, at the same EON + EOFF (43.8 mJ/cm2), the proposed FD-IGBT reduces dICE/dt by 88.2 % compared to conventional IGBTs. At the same dICE/dt (2.1 kA/μs), it reduces EON + EOFF by 53.4 %. Furthermore, the short-circuit withstand time (TSC) of the proposed device is improved by 169 % compared to conventional IGBTs.
一种新型双自偏置浮动肖特基二极管FD-IGBT
本文提出了一种新型的浮动假人IGBT (FD-IGBT),它集成了N型和p型肖特基势垒二极管(sbd),并通过仿真研究了其性能。在瞬态导通过程中,浮动p基区空穴的积累提高了其准费米势,触发两个串联sbd的导通,从而箝位浮动p基区的电压。该机制有效地降低了米勒电容,并显著抑制了从浮p基区到栅极的反向栅极充电电流。这减少了导通能量损失(EON),提高了dICE/dt的可控性。在短路条件下,sdd自适应导通,提高了短路容限时间(TSC)。在关闭状态下,sbd加速了井眼提取,减少了关闭时间和能量损失(EOFF)。TCAD仿真表明,在相同的EON + EOFF (43.8 mJ/cm2)下,FD-IGBT比传统的igbt减少了89.2%的dICE/dt。在相同的dICE/dt (2.1 kA/μs)下,使EON + EOFF降低53.4%。此外,与传统igbt相比,该器件的抗短路时间(TSC)提高了169%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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