A SP-SECE None-Residual Charge PEH Interface Circuit With an Optimized Phase Delay

Abstract

Self-Powered Synchronous Electric Charge Extraction (SP-SECE) suffers from the inherent phase inconsistency between the switching instant, which manipulates the voltage, and the moment of zero-crossing of the piezoelectric current. This degrades its energy extraction efficiency of it. This paper proposes a novel SP-SECE circuit to improve the Phase Delay (PD) introduced by Voltage Retreatment (VR) and Residual Charge (RC) left on the Piezoelectric Energy Harvester (PEH) capacitor after completion of SECE execution. To address the VR effect, the circuit employs a new reference branch, which can improve the timing of the SECE action. The RC issue is mitigated using a low-power sub-circuit, which removes the remaining charge on the PEH capacitor after each energy extraction. Post-layout simulations of the proposed circuit in a standard 180-nm CMOS technology verify that the losses linked to PD introduced by VR and RC phenomena are significantly reduced, increasing the net output power. Moreover, the proposed circuit achieves an extraction efficiency of 82% and a FOM_MOPIR of 300% at a peak voltage of 3.3 V.