A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation

Abstract

Computing-in-memory (CIM) has recently gained significant attention as it achieves high energy efficiency and throughput for deep convolutional neural networks (DCNNs). In this brief, we present a static random access memory (SRAM) CIM macro aimed at improving the energy efficiency of edge devices when performing 8-b multiply-and-accumulate (MAC) operations. The proposed architecture implements the following: 1) a successive approximation register analog-to-digital converter (SAR ADC) readout circuit based on a weight-flip-store (WFS) coding scheme, where energy efficiency is improved by optimizing the quantized interval; 2) an input-relevant partial power-off digital-to-analog converter (P2O-DAC) using input bit-level sparsity to reduce power consumption; and 3) a pipeline structure for interleaving MAC computation and readout operation to minimize the redundancy when loading input data into the CIM array. Our proposed CIM macro is implemented in TSMC 40-nm CMOS technology. Postlayout simulation results show an average macro energy efficiency of 16.8 TOPS/W without input and weight value sparsity.