A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-11 DOI:10.1109/TVLSI.2024.3509439

Chenxi Chen;Jinhong Wang;Xueye Hu;Shubin Liu

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引用次数: 0

Abstract

In recent years, field-programmable gate arrays (FPGAs) have become critical computing resources, featuring higher levels of system integration and accelerated clocking speeds. FPGA-based systems face increasing challenges in maintaining power and signal integrity. Consequently, a flexible and efficient power supply monitor is essential for evaluating the system’s performance and reliability. We propose an integrated power monitoring scheme within an FPGA, enabling real-time evaluation of power supply signal integrity. The monitor employs a hybrid structure combining a ring oscillator (RO)-based monitor and a tapped delay line (TDL)-based monitor, featuring first-order noise shaping and explicit dynamic-element matching (DEM) in its quantization. We analyze the principle of operation of the hybrid monitor and present its implementation in FPGAs. Demonstrated in an AMD Kintex-7 FPGA, tests show a voltage resolution of at least

$12.96~\mu $

V and a precision of 8.03-

$\mu $

V rms, and the effective bandwidth (BW) of the monitor is 10 MHz. The monitor utilizes only conventional logic resources and is delivered as a soft logic core. It can be migrated to different FPGA platforms and custom-integrated circuits with greater flexibility and integration.

查看原文本刊更多论文

一种用于FPGA应用的基于ro - tdl的片上电压监测器

近年来，现场可编程门阵列（fpga）具有更高的系统集成度和更快的时钟速度，已成为关键的计算资源。基于fpga的系统在保持功率和信号完整性方面面临越来越大的挑战。因此，一个灵活、高效的电源监控系统是评估系统性能和可靠性的必要条件。我们提出了一种集成电源监控方案，可以实时评估电源信号的完整性。该监视器采用环振荡器（RO）监视器和抽头延迟线（TDL）监视器相结合的混合结构，具有一阶噪声整形和显式动态元素匹配（DEM）量化的特点。分析了混合监测仪的工作原理，并给出了其在fpga上的实现。在AMD Kintex-7 FPGA上进行了测试，测试结果表明，该显示器的电压分辨率至少为12.96~ $\mu $ V，精度为8.03 ~ $\mu $ V rms，有效带宽（BW）为10 MHz。监视器仅利用常规逻辑资源，并作为软逻辑核心交付。它可以迁移到不同的FPGA平台和定制集成电路，具有更大的灵活性和集成度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.