A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2025-01-03 DOI:10.1109/TVLSI.2024.3520588

Xueyong Zhang;Yong-Jun Jo;Tony Tae-Hyoung Kim

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引用次数: 0

Abstract

Implementing parallel computing inside memory units, compute-in-memory (CIM) has shown significant energy and latency reduction, which are suitable for neural network accelerators, especially for low-power edge devices. This brief presents a compact 2T-eDRAM CIM structure to support signed 4b/4b/6b input/weight/output precision multiply-accumulate (MAC) operation, exploring a near-zero-skipping (NZS) technique to improve energy efficiency further and reduce weight update time. The center weight first (CWF) update method is proposed to extend the overall weight retention time. Furthermore, the analog multiplication and accumulation nonlinear compensation techniques are employed to improve the accuracy and linear range. Fabricated in 65-nm CMOS technology, this chip achieves the weight bit storage density of 3.7 Mb/mm2 and SWaP figure of merit of 210 TOPS/W Mb/mm2. The measured energy efficiency shows an average of 55.8 TOPS/W with the 4b/4b/6b input/weight/output precision at 1.2 V and 100 MHz.

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65纳米55.8 tops /W紧凑型2T edram内存宏与线性校准

内存计算（CIM）在内存单元内实现并行计算，显示出显著的能量和延迟降低，适用于神经网络加速器，特别是低功耗边缘设备。本文介绍了一种紧凑的2T-eDRAM CIM结构，该结构支持signed 4b/4b/6b输入/权重/输出精度乘法累加（MAC）操作，探索了一种近零跳变（NZS）技术，以进一步提高能源效率并减少权重更新时间。提出了中心权重优先（CWF）更新方法，以延长总权重保持时间。此外，采用模拟量乘法和累积非线性补偿技术，提高了测量精度和线性范围。该芯片采用65纳米CMOS工艺制造，重量位存储密度为3.7 Mb/mm2， SWaP性能值为210 TOPS/W Mb/mm2。测量的能量效率显示，在1.2 V和100 MHz下，4b/4b/6b输入/重量/输出精度平均为55.8 TOPS/W。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.