An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-04 DOI:10.1109/TVLSI.2024.3504539

Hayoung Lee;Juyong Lee;Sungho Kang

{"title":"An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory","authors":"Hayoung Lee;Juyong Lee;Sungho Kang","doi":"10.1109/TVLSI.2024.3504539","DOIUrl":null,"url":null,"abstract":"With the rapid advances in artificial intelligence (AI), the demand for data-intensive analytics has surged. Consequently, extensive research on AI acceleration has been conducted to enhance AI performance. Processing-in-memory (PiM) has emerged as a promising AI acceleration architecture, offering an unprecedented high-bandwidth connection between compute and memory. However, integrating many components in PiM can lead to yield degradation. To address this issue, we propose an efficient test architecture that utilizes a hybrid built-in self-test (BIST) for PiM. This architecture utilizes the structural and operational characteristics of PiM to facilitate testing. It can execute testing through the existing functional paths without requiring any additional hardware implementation in PiM. Furthermore, it achieves a 100% test coverage with the small number of test patterns. In addition, the functionality of self-test can be realized for PiM through reconfiguration of the existing hardware, resulting in a very small area overhead.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":"33 5","pages":"1452-1456"},"PeriodicalIF":2.8000,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10777846/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

With the rapid advances in artificial intelligence (AI), the demand for data-intensive analytics has surged. Consequently, extensive research on AI acceleration has been conducted to enhance AI performance. Processing-in-memory (PiM) has emerged as a promising AI acceleration architecture, offering an unprecedented high-bandwidth connection between compute and memory. However, integrating many components in PiM can lead to yield degradation. To address this issue, we propose an efficient test architecture that utilizes a hybrid built-in self-test (BIST) for PiM. This architecture utilizes the structural and operational characteristics of PiM to facilitate testing. It can execute testing through the existing functional paths without requiring any additional hardware implementation in PiM. Furthermore, it achieves a 100% test coverage with the small number of test patterns. In addition, the functionality of self-test can be realized for PiM through reconfiguration of the existing hardware, resulting in a very small area overhead.

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基于混合内建自检的高效内存处理测试体系结构

随着人工智能（AI）的快速发展，对数据密集型分析的需求激增。因此，人们对人工智能加速进行了广泛的研究，以提高人工智能的性能。内存处理（PiM）已经成为一种很有前途的人工智能加速架构，它在计算和内存之间提供了前所未有的高带宽连接。然而，在PiM中集成许多组件会导致成品率下降。为了解决这个问题，我们提出了一种有效的测试体系结构，它利用PiM的混合内置自检（BIST）。该体系结构利用PiM的结构和操作特性来促进测试。它可以通过现有的功能路径执行测试，而不需要在PiM中进行任何额外的硬件实现。此外，它用少量的测试模式实现了100%的测试覆盖率。此外，可以通过重新配置现有硬件来实现PiM的自检功能，从而产生非常小的面积开销。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.