De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-17 DOI:10.1109/TVLSI.2024.3513478

Hossein Eslahi;Stavroula Kapoulea;Zeeshan Ali;Mohammed Waqas Mughal;Farman Ullah;Meraj Ahmad;Martin Weides;Hadi Heidari

引用次数: 0

Abstract

This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of

$\text {IIP3}=10.46~\text {dBm}$

, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.

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工艺变化下有源滤波器线性特性的去嵌入方法

本文介绍了一种通过精确表征片上滤波器的带通和阻带传递函数（TF）来表征片上滤波器线性度的新方法。与传统方法不同，该方法仅使用一个缓冲器，简化了设计并提高了精度。滤波器和缓冲器采用GlobalFoundries (GF) 22nm FDX技术设计，在缓冲器设计中加入了一个反向偏置调谐机制，旨在保持缓冲器在工艺变化下的性能。后置仿真表明，该方法的线性度为$\text {IIP3}=10.46~\text {dBm}$，与独立滤波器的线性度相比，精度达到99.4%。类似的一致性在各个过程角落都可以观察到。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.