On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-24 DOI:10.1109/TVLSI.2024.3515110

Yoomi Park;Sangjin Byun

引用次数: 0

Abstract

In this brief, we discuss the merits of using nMOS-pMOS (NP)-type cells instead of nMOS-nMOS (NN)- or pMOS-pMOS (PP)-type cells in a single-ended, threshold-voltage compensated CMOS RF-dc rectifier. By adopting the NP-type cells, we can avoid the degradation of the generated output dc voltage due to parasitic long interconnection wire capacitance, deep N-well to P-substrate junction capacitance, and additional body effect. For comparison, we have implemented two RF-dc rectifiers in a 28-nm 1P11M CMOS process. The measured results show that the implemented RF-dc rectifier with the NP-type cells achieves 0.7-dB higher input power sensitivity and

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faster recharging time than the other rectifier with the NN-type cells.

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在阈值电压补偿CMOS RF-DC整流器中使用nmos - pmos型电池的研究

在本文中，我们讨论了在单端阈值电压补偿的CMOS RF-dc整流器中使用nMOS-pMOS （NP）型电池代替nMOS-nMOS （NN）或pMOS-pMOS （PP）型电池的优点。通过采用np型电池，我们可以避免由于寄生的长互连线电容、深n -阱到p -衬底结电容以及附加的体效应而产生的输出直流电压的退化。为了比较，我们在28纳米1P11M CMOS工艺中实现了两个RF-dc整流器。实测结果表明，采用np型电池的RF-dc整流器的输入功率灵敏度比采用nn型电池的整流器高0.7 db，充电时间比采用nn型电池的整流器快3倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.