ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling

Abstract

Timing error prediction circuits have demonstrated greater efficiency in reducing the worst case timing margins of conventional circuits. However, prior works of timing error prediction circuits have complicated the clock tree or introduced a substantial number of delay cells along data paths, resulting in a considerable increase in area overhead. This work introduces asynchronous timing error prediction circuit (ATEP), an ATEP that integrates timing error prediction technology with bundle-data asynchronous templates. The proposed circuit leverages delay lines in the request wire to generate the warning detection window (WDW) independent of clock signals, thereby reducing area overhead and streamlining the clock tree. In addition, we present an adaptive voltage and frequency scaling (AVFS) controller, which evaluates the likelihood of warnings or the quantity of warning paths based on path activation rates to determine when to cease adjustments. This strategy helps to identify the frequency closer to the point of first failure (PoFF). Furthermore, we propose a dynamic warning detector gating strategy to gate warning detectors based on the current environment, further decreasing power consumption. Implementing this circuit on an RISC-V processor, targeting 28-nm CMOS technology, yields up to a 56.8% performance improvement with only a 3.79% area cost and up to a 28.0% reduction in power consumption.