Sign-Off Timing Considerations via Concurrent Routing Topology Optimization

IF 2.7 3区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Siting Liu;Ziyi Wang;Fangzhou Liu;Yibo Lin;Bei Yu;Martin D. F. Wong
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引用次数: 0

Abstract

Timing closure is considered across the circuit design flow. Generally, the early stage timing optimization can only focus on improving early timing metrics, e.g., rough timing estimation using linear RC model or prerouting path length, since obtaining sign-off performance needs a time-consuming routing flow. However, there is no consistency guarantee between early stage metrics and sign-off timing performance. Therefore, we utilize the power of deep learning techniques to bridge the gap between the early stage analysis and the sign-off analysis. A well-designed deep learning framework guides the adjustment of Steiner points to enable explicit early stage timing optimization. Cooperating with deep Steiner point adjustment, we propose the routing topology reconstruction to accelerate the convergence and hold a reasonable routing topology. Further, we also introduce Steiner point simplification as a post-processing technique to avoid unnecessary routing constraints. This article demonstrates the ability of the learning-assist framework to perform robust and efficient timing optimization in the early stage with comprehensive and convincing experimental results on real-world designs. With Steiner point adjustment alone, TSteinerPt, can help the state-of-the-art open-source router to obtain 11.2% and 7.1% improvement for the sign-off worst-negative slack and total negative slack, respectively. Under the additional joint optimization with routing topology reconstruction and simplification, TSteinerRec can further save 25.9% optimization duration with a better-sign-off performance.
通过并行路由拓扑优化考虑签收时间因素
时序闭合在整个电路设计流程中都要考虑。通常,早期的时序优化只能专注于改善早期的时序指标,例如,使用线性RC模型或预路由路径长度进行粗略的时序估计,因为获得签到性能需要一个耗时的路由流。然而,在早期阶段度量和签收时间性能之间没有一致性保证。因此,我们利用深度学习技术的力量来弥合早期分析和最终分析之间的差距。精心设计的深度学习框架指导斯坦纳点的调整,以实现明确的早期时序优化。结合深度施泰纳点调整,提出路由拓扑重构方案,加快收敛速度,保持合理的路由拓扑。此外,我们还引入了斯坦纳点简化作为后处理技术,以避免不必要的路由约束。本文展示了学习辅助框架在早期阶段进行鲁棒和有效的时序优化的能力,并在现实世界的设计中得到了全面和令人信服的实验结果。仅通过Steiner点调整,TSteinerPt可以帮助最先进的开源路由器在签收最坏负松弛和总负松弛上分别获得11.2%和7.1%的改进。在路由拓扑重构和简化的附加联合优化下,TSteinerRec可以进一步节省25.9%的优化时间,并具有更好的签入性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
CiteScore
5.60
自引率
13.80%
发文量
500
审稿时长
7 months
期刊介绍: The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components. The aids include methods, models, algorithms, and man-machine interfaces for system-level, physical and logical design including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, hardware-software co-design and documentation of integrated circuit and system designs of all complexities. Design tools and techniques for evaluating and designing integrated circuits and systems for metrics such as performance, power, reliability, testability, and security are a focus.
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