Negative capacitance FinFETs for low power applications: A review

Abstract

One of the most crucial factors that dictate the current-voltage (I–V) behavior of metal oxide semiconductor field-effect transistors (MOSFETs) is the source-to-drain barrier under the control of the gate voltage, V_G. Boltzmann statistics predict that the gate voltage for a conventional MOSFET has to be as high as 60 mV to increase the magnitude of the current by a factor of ten. This “Boltzmann tyranny” puts a minimum voltage limit on the threshold voltage at about 0.3 V while preserving an on-off current ratio of five decades, I_on/I_off. In IoT (Internet of Things), where the dissipation of power is critical, devices that reduce the subthreshold swing are extremely desirable to ensure efficient computation. NC FinFETs have proven to be one of the more promising areas of research as they exhibit the potential to benefit from simplified fabrication, seamless process integration, suppression of SCEs, and better current drive through a lower subthreshold swing. This article provides an in-depth examination of the state-of-the-art in NC FinFET technology with regard to improvements in the most critical device parameters such as drain current, switching ratio, subthreshold swing, and hysteresis. Furthermore, a comparative analysis of various NC FinFETs for low-power applications, and a summary of the findings from multiple criteria such as fabrication feasibility and design constraints are given.