Accelerating Control Flow on CGRAs via Speculative Iteration Execution

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-03-26 DOI:10.1109/LCA.2025.3554777

Heng Cao;Zhipeng Wu;Dejian Li;Peiguang Jing;Sio Hang Pun;Yu Liu

引用次数: 0

Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) offer a promising architecture for accelerating general-purpose, compute-intensive tasks. However, handling control flow within these tasks remains a challenge for CGRAs. Current methods for handling control flow in CGRAs execute condition operations before selecting branch paths, which adds extra execution time. This article proposes a CGRA architecture that decouples the control flow condition and path selection within an iteration through speculative iteration execution (SIE), where the condition is predicted before the start of the current iteration. Compared to existing methods, the SIE CGRA achieves a geometric mean speedup of

$1.31\times$

over Partial Predication,

$1.17 \times$

over Dynamic-II Pipeline and

$1.12\times$

over Dual-Issue Single-Execution.

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通过推测迭代执行加速CGRAs控制流

粗粒度可重构数组（CGRAs）为加速通用的计算密集型任务提供了一种很有前途的体系结构。然而，在这些任务中处理控制流对CGRAs来说仍然是一个挑战。当前CGRAs中处理控制流的方法在选择分支路径之前执行条件操作，这增加了额外的执行时间。本文提出了一种CGRA架构，该架构通过推测迭代执行（SIE）将控制流条件和迭代中的路径选择解耦，其中在当前迭代开始之前预测条件。与现有方法相比，SIE CGRA的几何平均加速速度比部分预测提高1.31倍，比Dynamic-II Pipeline提高1.17倍，比Dual-Issue Single-Execution提高1.12倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.