A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-04-14 DOI:10.1016/j.mejo.2025.106674

Zhangqing He , Junming Zhang , Xinrui Zhu , Siyu Luo , Zhengya Zhang , Zhou Huang

{"title":"A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security","authors":"Zhangqing He , Junming Zhang , Xinrui Zhu , Siyu Luo , Zhengya Zhang , Zhou Huang","doi":"10.1016/j.mejo.2025.106674","DOIUrl":null,"url":null,"abstract":"<div><div>Physical unclonable function is considered a promising hardware security primitive for resource-constrained IoT devices. Arbiter PUF is one of the most well-known strong PUFs, which suffers from vulnerability to machine learning attacks and low reliability. In this paper, a high reliability and machine learning resistant cross-matrix (CM) arbiter PUF is proposed, which realizes the diversity of signal transmission paths through interstage cross structures, and adds inter row cross-feed loops between different arbiter PUFs to nonlinearized the circuit, which considerably enhances the resistance to machine learning attacks. A reliability enhancement model is also proposed to select the pair with the largest delay difference as the output from multiple delay paths, which significantly improves the reliability of CMAPUF. A mathematical model is developed to analyze the proposed CMAPUF and then we implement the circuit on Xilinx Artix-7 FPGA. The test results show that CMAPUF can effectively resist several widely used machine learning attacks with prediction accuracy below 60 % under 10<sup>6</sup> training samples, while its bit error rate (BER) at normal condition (1V, 25 °C) is 0.55 % and worst BER when the environmental change is 1.56 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106674"},"PeriodicalIF":1.9000,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001237","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Physical unclonable function is considered a promising hardware security primitive for resource-constrained IoT devices. Arbiter PUF is one of the most well-known strong PUFs, which suffers from vulnerability to machine learning attacks and low reliability. In this paper, a high reliability and machine learning resistant cross-matrix (CM) arbiter PUF is proposed, which realizes the diversity of signal transmission paths through interstage cross structures, and adds inter row cross-feed loops between different arbiter PUFs to nonlinearized the circuit, which considerably enhances the resistance to machine learning attacks. A reliability enhancement model is also proposed to select the pair with the largest delay difference as the output from multiple delay paths, which significantly improves the reliability of CMAPUF. A mathematical model is developed to analyze the proposed CMAPUF and then we implement the circuit on Xilinx Artix-7 FPGA. The test results show that CMAPUF can effectively resist several widely used machine learning attacks with prediction accuracy below 60 % under 10⁶ training samples, while its bit error rate (BER) at normal condition (1V, 25 °C) is 0.55 % and worst BER when the environmental change is 1.56 %.

查看原文本刊更多论文

一种具有高可靠性和抗ml的跨矩阵仲裁PUF，用于物联网设备安全

对于资源受限的物联网设备，物理不可克隆功能被认为是一种很有前途的硬件安全原语。仲裁者PUF是最著名的强PUF之一，它存在容易受到机器学习攻击和可靠性低的问题。本文提出了一种高可靠性和抗机器学习的交叉矩阵（CM）仲裁PUF，通过级间交叉结构实现信号传输路径的多样性，并在不同仲裁PUF之间增加行间交叉馈电回路，使电路非线性化，大大提高了抗机器学习攻击的能力。提出了一种可靠性增强模型，从多个延迟路径中选择时延差最大的对作为输出，显著提高了camapuf的可靠性。通过建立数学模型对该电路进行分析，并在Xilinx Artix-7 FPGA上实现。测试结果表明，在106个训练样本下，该算法能够有效抵御几种常用的机器学习攻击，预测准确率在60%以下，正常情况下（1V, 25°C）误码率为0.55%，环境变化时的误码率为1.56%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.