One-Sided Schmitt Trigger-Based 11T Carbon Nanotube Field Effect Transistor—Based Static Random-Access Memory Cell for Modern IoT Embedded Devices at 32 nm Technology

Abstract

Researchers are working to develop a static random-access memory (SRAM) cell that consumes less power, is highly stable, and operates at high speed. This paper proposes a new one–sided Schmitt-trigger based 11 transistor (ST11T) SRAM cell using carbon nanotube field effect transistors (CNTFET) with the loop cutting transistor technique. The ST inverter, along with the read decoupled and loop cutting technique, leads to low power consumption, better stability, and low access times during its operation modes. Simulation results conducted using the Stanford university 32 nm CNTFET technology in the HSPICE simulator with V_DD = 0.9 V demonstrate that the proposed ST11T shows an improvement of 99.9% in hold power compared to CONV6T, DBB7T, and CONV8T designs. The proposed cell's topology achieves a remarkable 99.9% improvement in read power compared to all the cells analyzed in this study and demonstrates a significant 96.96% enhancement in write power efficiency when compared to the SPI11T design. Also, the WSNM/RSNM of the cell is witnessed to improve by 1.35X/1.58X times its CONV6T counterpart and hence improving its stability In the nanometer regime, variations in process, voltage, and temperature (PVT) significantly impact performance parameters such as power, stability, and delay. The proposed ST11T SRAM cell has been evaluated under PVT variations and compared with state-of-the-art SRAM cells used in this study. Results indicate that the proposed SRAM cell exhibits exceptional stability and reliability despite PVT fluctuations. These simulations confirm the effectiveness and efficiency of the ST11T SRAM cell, positioning it as a highly suitable option for modern IoT embedded devices.