A 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams in 55-nm CMOS Technology

Abstract

This paper demonstrates a 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams. The full-connected multibeam architecture is adopted to maximize the beamforming gain. To mitigate the design complexity and large chip area-consumption caused by the multibeam combination, a compact active multibeam combining technique is proposed, which features current-domain phase shifted signal combining and compact passive signal connection network. Implemented in a 55-nm CMOS process, the receiver consumes a current of 1100 mA with a 1.2 V supply. From 10 to 15 GHz, the receiver achieves a 360° phase shifting range with a 6-bit resolution, and the root mean square (RMS) phase is less than 3°. The 6-bit attenuator in each output channel achieves less than 0.4 dB root mean square (RMS) gain error. The receiver demonstrates a gain of 20 dB (20.5 dB), a 5.5 dB (7.6 dB) noise figure, and an input-referred 1 -dB gain compression point (IP_1dB) of −20 dBm (−22 dBm) at 10 GHz (15 GHz), respectively. The chip size, including pads, is only 3.6 × 5.4 mm².