A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-04-10 DOI:10.1016/j.mejo.2025.106664

Annan Wang , Yuchen Sun , Zhang Zhang

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引用次数: 0

Abstract

This article presents a low-power CMOS voltage reference circuit with process and temperature compensation. The design employs a current source circuit to generate a bias current that shows process and temperature variations complementary to those of the output voltage of the stacked diode connected MOS transistor (SDMT). By adjusting the transistor size and current mirror ratio, the bias current exhibits the opposite temperature coefficient (TC) and process skew to that of the SDMT, thus achieving process and temperature compensation. This voltage reference is implemented using a standard 65 nm CMOS process, with a core chip area of

5500 μ m^{2}

. At room temperature, measurements were taken on 18 chips, with an average output reference voltage of 335.7 mV and a standard deviation of 1.02 mV (

σ

μ

= 0.31%). Over the temperature range of −40 °C to 120 °C, the average temperature coefficient is 59 ppm/

^{\circ}

C. Within the supply voltage range of 0.7 V–1.5 V, the line sensitivity is 0.21%/V, the power supply rejection ratio (PSRR) at 100 Hz is −50 dB, and the power consumption at 0.7 V is 15.4 nW.

查看原文本刊更多论文

15.4 nW， 59 ppm/ C的CMOS电压基准电路，带有工艺和温度补偿

本文介绍了一种具有工艺和温度补偿的低功耗CMOS电压基准电路。该设计采用电流源电路产生偏置电流，显示与堆叠二极管连接的MOS晶体管（SDMT）输出电压互补的工艺和温度变化。通过调整晶体管尺寸和电流反射比，使偏置电流表现出与SDMT相反的温度系数（TC）和工艺偏差，从而实现工艺和温度补偿。该电压基准采用标准的65 nm CMOS工艺实现，核心芯片面积为5500μm2。在室温下，在18个芯片上进行测量，平均输出参考电压为335.7 mV，标准差为1.02 mV （σ/μ = 0.31%）。在−40°C至120°C的温度范围内，平均温度系数为59 ppm/ C。在0.7 V ~ 1.5 V供电电压范围内，线路灵敏度为0.21%/V， 100 Hz时电源抑制比PSRR为−50 dB， 0.7 V时功耗为15.4 nW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.