A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-04-08 DOI:10.1016/j.mejo.2025.106685

Lin Wu , Lichen Feng , Yunlong Liu , Libo Qian , Yinshui Xia , Zhangming Zhu

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引用次数: 0

Abstract

Numerous SRAM-based analog Computing-In-Memory (CIM) macros have been verified in silicon to show great energy efficiency improvement. However, the large area of the existing analog-digital-converters (ADCs), especially the wide pitches between the ADCs, limit the number of computing results that can be quantized and readout in parallel. In this paper, we propose a 2.9 μm-pitch 4.3fJ/conv 6-bit SAR ADC in 28 nm CMOS process. The area and power consumption of the complete ADC are significantly decreased by improving the finger-type differential capacitor in the unit-length DAC technology, and using the improved clock generation circuit and fully dynamic latch in the Vcm-based switching scheme. The proposed ADC occupies only 0.000159 mm² with the pitch of 2.9 μm, which can be aligned with as few bitcell columns as possible, showcasing superior potential for improving both throughput and energy efficiency of analog CIM macros.

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一个0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6位SAR ADC，用于内存中模拟SRAM计算的高吞吐量并行读出

许多基于 SRAM 的模拟计算内存（CIM）宏已在硅片中得到验证，显示出极大的能效改进。然而，现有模拟数字转换器（ADC）的大面积，特别是 ADC 之间的宽间距，限制了可量化和并行读出的计算结果的数量。本文提出了一种 2.9 μm 间距的 4.3fJ/conv 6 位 SAR ADC，采用 28 nm CMOS 工艺。通过改进单位长度 DAC 技术中的指型差分电容器，以及在基于 Vcm 的开关方案中使用改进的时钟发生电路和全动态锁存器，整个 ADC 的面积和功耗都大幅降低。所提出的 ADC 仅占 0.000159 mm2，间距为 2.9 μm，可与尽可能少的位元列对齐，在提高模拟 CIM 宏的吞吐量和能效方面展现了卓越的潜力。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.