A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS

Abstract

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) analog-to-digital converter (ADC)-digital signal processing (DSP)-based retimer transceiver for reaching-distance extension. An injection-locked oscillator (ILO)-based jitter-filtering clocking scheme with relaxed bandwidth limitation and low-power consumption is proposed to obtain synchronous low-jitter clocks. The transmitter (TX) utilizes an internal feed-forward equalizer (FFE) cascaded with a forward-coupling pad driver to improve the output inter-symbol interference (ISI) jitter, and a timing-optimized 4:1 multiplexer (MUX) to reduce the serialization jitter. The receiver (RX) combines a flexible continuous-time linear equalizer (CTLE), a signal-to-noise ratio (SNR)-optimized ADC with 8-bit quantization, and a high-resolution digital equalization to further minimize the bit-error rate (BER). Fabricated in a 28-nm CMOS process, the prototype transceiver achieves 1E-12 raw BER at 112 Gb/s while compensating 31.2-dB channel loss. The clock network delivers a rms recovered clock jitter of 252 fs and a power efficiency of 0.56 pJ/bit, which outperforms other state-of-the-art works.