A Watt-Level, 3.3-V Triple-Stack Switched Capacitor Digital PA in FinFET Technology

Abstract

This work proposes and analyzes a new circuit topology that enables reliable triple-transistor stacking in the switched-capacitor digital power amplifier (SC-DPA) working from a 3.3-V supply, about three times the process maximum allowed voltage across the transistor nodes ( $V_{D,\text {Max}}$ ). The proposed topology employs capacitive feedback (CF) to meet device voltage constraints. Higher supply voltage usage results in reduced supply ripples and improved memory effects while allowing higher power watt-level SC-DPA. A 5–7-GHz, dual-core Doherty-like combining SC-DPA prototype was implemented and integrated into an all-digital polar transmitter (DPTX) using 16-nm FinFET CMOS technology. The SC-DPA demonstrates a maximum power ( $P_{\max }$ )/power efficiency (PE) of 30.15 dBm/34.7% at 5.2 GHz. An error vector magnitude (EVM)/power consumption of −38 dB/830 mW is measured at 6.1-GHz and 9-dB BO (dBBO) from $P_{\max }$ , thus meeting MCS13 4096-QAM OFDM Wi-Fi7 requirement. The high-temperature operating life (HTOL) accelerating aging test was performed showing the ability to meet the expected lifetime of the device with only 0.5-dB $P_{\max }$ degradation.