Overcoming Welding and Contact Degradation Failures Incurred by Complementary N/MEMS Logic Gate Structures Fabricated on SOI Wafers

Abstract

Nano/microelectromechanical systems (N/MEMS) based complementary logic circuits offer a physically robust alternative to conventional CMOS control systems, which are able to function in environments unsuitable for transistor devices. In this work we demonstrate novel, configurable, complementary logic circuits comprised entirely of relays at both NEMS and MEMS scale, which are capable of fulfilling all primary logic functions. Lifetime testing of the fabricated devices revealed two key failure modes: contact degradation and welding of high voltage cantilevers, both of which are caused by the charging and discharging of unwanted parasitic capacitances inherent to complementary relay structures. Devices are consequently damaged by high transient current and arc discharge between contacts. Several solutions are proposed and implemented to mitigate these issues, including minimization of unwanted capacitances, optimization of metallization scheme, introduction of intermediate operation cycles intended to increase time between state changes, and prevention of welding by preemptively charging capacitors to an intermediate voltage. To this effect, a detailed study of lifetimes for both single cantilevers and logic gate structures is presented comparing a variety of metallization schemes using Pt, Ti, TiN, and W, including their multilayer combinations. These varied optimization methods yielded single cantilever lifetimes of 1.74 billion cycles on average for devices with a Ti adhesion layer, a Pt primary layer, and a W surface layer to increase durability. Using the same metallization scheme, complementary logic structures achieved 0.6 million cycles on average. These results demonstrate the viability of robust N/MEMS based complementary logic circuits for safety critical control applications.[2024-0203]