High-speed convolutional neural networks using parallel prefix adders

Abstract

Many deep learning applications, particularly image processing, frequently utilize convolutional neural networks (CNNs) due to their remarkable accuracy. However, the heavy computational demands of CNNs pose a challenge for high-speed applications. First, this work introduces a delay efficient hybrid-parallel prefix adder (HPPA) where the total delay is minimized by changing black and gray cell paths. The proposed adder achieves lowest delay compared to the other available PPA adders. It achieves 10.64% reduction in total delay compared to recent PPA Adders. Secondly, we have employed the proposed HPPA adder to obtain a high-speed LeNet CNN architecture. Integration of the proposed hybrid adder into the LeNet CNN architecture significantly reduces the delay in the convolution layer. FPGA implementations of the proposed PPA adder and convolutional layer of LeNet architecture are performed. The proposed PPA adder achieves a 3.05% delay improvement while the critical path delay of the LeNet CNN is reduced by 16.78% compared to the relevant implementations. The implemented LeNet architecture using the proposed delay-efficient PPA adder offers a promising solution for deploying CNNs at high speed applications.