Lateral Si/Si1-xGex/Si Channel Heterostructure Charge Plasma Nanowire JLFET to Eliminate the Effects of Variation of Geometrical Dimensions

Abstract

In this article, a charge plasma (CP) based doping-less (DL) nanowire junctionless field effect transistor (NW JLFET) has been investigated for better immunity against geometrical dimension variation from a low power application perspective. SiGe source/drain and Si/SiGe/Si heterostructure channel have been used to improve the electrostatics in the channel to reduce the leakage current. With this doping-less structure, the concept of charge plasmas has been incorporated by selecting electrodes with appropriate work functions. In addition to a low thermal budget, the doping-less devices are easier to fabricate, have a reduced random fluctuation effect, and offer a low cost per unit. The doping-less structure also offers improved mobility and higher current flow. The proposed device is compared with the conventional SiGe nanowire junctionless FET. When both devices are compared, lateral Si/SiGe/Si CP DL NW JLFET shows fewer changes in geometrical dimension variation in terms of germanium content x, nanowire thickness (t_si) and doping profile (N_d) on the drain current (I_DS), I_ON/I_OFF ratio, threshold voltage (Vth), drain-induced barrier lowering (DIBL), and subthreshold slope (SS). A drain current model for lateral Si/SiGe/Si CP DL NW JLFET has also been developed in this paper, which includes the impact of the charge plasma technique. The impact of geometrical dimension variation on the analog characteristics of both devices has been studied in terms of like transconductance (g_m) and transconductance gain factor (TGF) (g_m/I_DS). Thus, in the lateral Si/SiGe/Si CP DL NW JLFET, the charge plasma technique along with channel engineering solves the problem of geometrical dimension variation without affecting the inherited properties of junctionless devices.