A 10-bit 4 GS/s Pipelined-SAR ADC based on loop-unrolled and partial-interleaving

Abstract

This paper presents a 4 GS/s 10-bit pipelined-SAR ADC that integrates loop-unrolled (LU) and partial-interleaving (PI) techniques. In the first stage, the LU SAR ADC quantizes the initial 3 bits, enabling a high-speed and efficient quantization process. The residue voltage is then sampled through passive residue transfer and amplified by a two-stage inverter-based residue amplifier, achieving almost 66 % speed enhancement by allowing the first-stage ADC to operate in parallel with the interstage amplifier. The amplified residue voltage is subsequently quantized by the second stage, which consists of a 4-channel time-interleaved SAR ADC, to generate the remaining 8-bit digital code. Post-simulation results demonstrate an SNDR of 57.4 dB and an SFDR of 70.63 dB at the Nyquist frequency.