Loop-Unrolled SAR ADC With Complementary Voltage-to-Time Converters

IF 0.7 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Electronics Letters Pub Date : 2025-04-05 DOI:10.1049/ell2.70242

Da-Yeon Kim, Sang-Won Oh, Hyeon-Gi Hwang, Young-Seung Kim, Dong-Ryeol Oh

引用次数: 0

Abstract

A 6-bit asynchronous loop-unrolled (LU) successive approximation register (SAR) analogue-to-digital converter (ADC) with a complementary voltage-to-time converter (CVTC) and the efficient latch technique needed for this structure are proposed. The proposed structure utilises CVTC to reduce the power consumed by the reset operation and halves the operating frequency of the CVTC. Designed with a 500-nm CMOS process, the 6-bit 10-MS/s LU SAR ADC shows a power saving of 23.66% compared to the VTC-based LU SAR ADC.

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带互补电压-时间转换器的环展开SAR ADC

提出了一种具有互补电压-时间转换器（CVTC）的6位异步环展开（LU）逐次逼近寄存器（SAR）模数转换器（ADC）以及该结构所需的高效锁存技术。建议的结构利用CVTC来减少复位操作所消耗的功率，并将CVTC的工作频率减半。采用500纳米CMOS工艺设计的6位10 ms /s LU SAR ADC，与基于vtc的LU SAR ADC相比，功耗节省23.66%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Electronics Letters 工程技术-工程：电子与电气

CiteScore

2.70

自引率

0.00%

发文量

268

审稿时长

3.6 months

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