SDT: Cutting Datacenter Tax Through Simultaneous Data-Delivery Threads

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Amin Mamandipoor;Huy Dinh Tran;Mohammad Alian
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引用次数: 0

Abstract

Networking is considered a datacenter tax, and hyperscalers push hard to provide high-performance networking with minimal resource expenditure. To keep up with the ever-increasing network rates, many CPU cycles are spent on the networking tax. We make a key observation that network processing threads can be simultaneously executed on server CPUs with minimal interference with the application threads. However, utilizing simultaneous multithreading (SMT) to scale the number of network threads with the number of application threads suffers from (1) failing to provide strict tail latency requirements for latency-critical applications, and (2) reducing the number of available hardware threads for application processes, thus contributing to a high datacenter network tax. In this work, we design, implement, and evaluate a chip-multiprocessor (CMP) with specialized Simultaneous Data-delivery Threads (SDT) per physical core. The key insight is that with judicious partitioning at the architectural level, SDT can safely co-run with application processes with guaranteed performance isolation. Our evaluation results, using full-system simulation, show that a 20-core CMP enhanced with SDT reduces the area and power consumption of a baseline 40-core CMP by 47.5% and 66%, respectively, while reducing network throughput by less than 10%.
SDT:通过同步数据传递线程减少数据中心的税收
网络被认为是数据中心的一项税收,超大规模企业努力以最小的资源支出提供高性能网络。为了跟上不断增长的网络速率,许多CPU周期都花在了网络开销上。我们发现,网络处理线程可以在服务器cpu上同时执行,对应用程序线程的干扰最小。但是,利用同步多线程(SMT)根据应用程序线程的数量来扩展网络线程的数量会遇到以下问题:(1)无法为延迟关键型应用程序提供严格的尾部延迟要求;(2)减少了应用程序进程可用的硬件线程的数量,从而导致数据中心网络开销很高。在这项工作中,我们设计、实现和评估了一个芯片多处理器(CMP),每个物理核心都有专门的同步数据传递线程(SDT)。关键的见解是,通过在体系结构级别进行明智的分区,SDT可以安全地与应用程序进程协同运行,并保证性能隔离。我们使用全系统仿真的评估结果表明,与基线40核CMP相比,使用SDT增强的20核CMP的面积和功耗分别减少了47.5%和66%,而网络吞吐量减少了不到10%。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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