Guido Di Patrizio Stanchieri , Orazio Aiello , Andrea De Marcellis
{"title":"A reduced effort design, low power, extremely compact, CMOS ADC based on voltage-to-time converter","authors":"Guido Di Patrizio Stanchieri , Orazio Aiello , Andrea De Marcellis","doi":"10.1016/j.aeue.2025.155790","DOIUrl":null,"url":null,"abstract":"<div><div>A low-effort, tiny, low-power, inverter-based Analog-to-Digital Converter (ADC) is proposed in this paper. Based on a Voltage-to-Time Converter (VTC), the architecture requires a minimum design adjustment of the core block to let it work across supply voltages down to 0.3 V. The operation is based on charging and discharging of a timing capacitor, which enables a square wave from a digital counter to be converted from voltage to pulse width as a function of the input voltage signal. In turn, the duty cycle makes counting an additional digital counter driven by a feasible ring oscillator. Post-layout simulations of the designed solution, which relies on TSMC 180 nm standard CMOS technology, show a Si area of 7200 µm<sup>2</sup>, a 6.8 ENOB, a power consumption of 409 nW, and a sample rate of 5 kS/s. These ADC’s extremely low voltage and low power features make it appropriate for energy-harvested Systems-on-Chips (SoCs) in biomedical and Internet of Things (IoT) applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"196 ","pages":"Article 155790"},"PeriodicalIF":3.0000,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Aeu-International Journal of Electronics and Communications","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1434841125001311","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A low-effort, tiny, low-power, inverter-based Analog-to-Digital Converter (ADC) is proposed in this paper. Based on a Voltage-to-Time Converter (VTC), the architecture requires a minimum design adjustment of the core block to let it work across supply voltages down to 0.3 V. The operation is based on charging and discharging of a timing capacitor, which enables a square wave from a digital counter to be converted from voltage to pulse width as a function of the input voltage signal. In turn, the duty cycle makes counting an additional digital counter driven by a feasible ring oscillator. Post-layout simulations of the designed solution, which relies on TSMC 180 nm standard CMOS technology, show a Si area of 7200 µm2, a 6.8 ENOB, a power consumption of 409 nW, and a sample rate of 5 kS/s. These ADC’s extremely low voltage and low power features make it appropriate for energy-harvested Systems-on-Chips (SoCs) in biomedical and Internet of Things (IoT) applications.
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