Qing Su , Xuan Guo , Hanbo Jia , Heping Ma , Linzhen Wu , Kai Sun , Xinyu Liu
{"title":"A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier","authors":"Qing Su , Xuan Guo , Hanbo Jia , Heping Ma , Linzhen Wu , Kai Sun , Xinyu Liu","doi":"10.1016/j.mejo.2025.106659","DOIUrl":null,"url":null,"abstract":"<div><div>—This work presents a single-channel, fully-dynamic SAR-assisted pipelined ADC that performs well over wide bandwidth. The ADC employs a dynamic, open-loop, two-stage cascade amplifier to realize 32x high-gain with efficient power. Meanwhile, the amplifier adopts strong output drive to reduce amplification time and still keeps good linearity. A parasitic optimized bootstrap switch is employed to enhance linearity for S/H at high speeds. It has also been explored several methods to shorten the turn-on paths of bootstrap switch in both schematic and layout. The prototype ADC was fabricated in a 28-nm process, it consumes 5.1-mW from 1V supply at 500 MS/s and occupies an area of 0.011-mm<sup>2</sup>. For 43.80 MHz input, the ADC achieves a SNDR of 58.2 dB and a SFDR of 71.9 dBc. With Nyquist input of 236.33 MHz, the measured SNDR and SFDR can have good performance of 56.3 dB and 69.4 dBc. This leads to a Schreier and a Walden figure-of-merit (FoM) values of 165.1 dB and 16.18 fJ/conv.-step, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106659"},"PeriodicalIF":1.9000,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001080","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
—This work presents a single-channel, fully-dynamic SAR-assisted pipelined ADC that performs well over wide bandwidth. The ADC employs a dynamic, open-loop, two-stage cascade amplifier to realize 32x high-gain with efficient power. Meanwhile, the amplifier adopts strong output drive to reduce amplification time and still keeps good linearity. A parasitic optimized bootstrap switch is employed to enhance linearity for S/H at high speeds. It has also been explored several methods to shorten the turn-on paths of bootstrap switch in both schematic and layout. The prototype ADC was fabricated in a 28-nm process, it consumes 5.1-mW from 1V supply at 500 MS/s and occupies an area of 0.011-mm2. For 43.80 MHz input, the ADC achieves a SNDR of 58.2 dB and a SFDR of 71.9 dBc. With Nyquist input of 236.33 MHz, the measured SNDR and SFDR can have good performance of 56.3 dB and 69.4 dBc. This leads to a Schreier and a Walden figure-of-merit (FoM) values of 165.1 dB and 16.18 fJ/conv.-step, respectively.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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