InAs Nanowires Elevated on Si(001) by Nanopedestals for CMOS-Compatible Fabrication

Abstract

Catalyst-free, selective growth of InAs nanowires (NWs) elevated on a Si(001) substrate by (111)-faceted nanopedestals for CMOS compatibility is investigated with molecular beam epitaxy. It begins with processing the planar substrate surface into an array of three-dimensional (3D) Si core–SiO₂ shell nanostructures, where each Si core has a lateral dimension of ∼50 nm and a height of ∼300 nm, analogous to a vertical pillar. A side edge of every core tip is treated with dry/wet etching through the SiO₂ shell film to fabricate a deep nanometer-scale (∼10 nm in both width and height), (111)-faceted nanopedestal. This provides a selective nucleation site of InAs for a position- and direction-controlled ∼1.2 μm-long, ∼55-nm-wide NW, axially along Si[111] and radially over a nearby SiO₂ shell. Relieving the misfit strain by the local compliance and edge-induced relaxation associated with its shape and size, the nanopedestal enhances the critical thickness dramatically in 3D modeling and provides an NW that can accommodate mechanical and structural impacts in the postgrowth process for CMOS compatibility. The postgrowth manipulation for planar processing and high-density integration by bending and segmentation is addressed.