A 500MS/s 9-bit two-step SAR ADC with loop-unrolling

Abstract

This paper introduces a passive transfer Two-Step asynchronous loop-unrolling successive approximation register analog-to-digital converter (Two-step LU-SAR ADC). The design employs a loop-unrolling architecture, which traditionally requires calibration operations for comparators that consume time allocated for quantization, thereby reducing speed. To address this issue, the calibration cycle of the second stage is deferred to the subsequent sampling instance by incorporating a pair of switches. This adjustment allows the entire holding time of the second stage to be dedicated to quantization. Furthermore, to overcome the comparison time limitations inherent in SAR ADCs, a novel double-tail comparator is proposed. This comparator initiates its comparison from a mid-voltage state, facilitating a faster determination of outcomes. The proposed ADC is operated at a supply voltage of 1.2 V when simulated using 65-nm CMOS technology. Post-layout simulation results demonstrate that, at a sampling speed of 500 MS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 53.08 dB, with a power consumption of 3.3 mW, and the figure of merit (FOMw) is 17.98 fJ/conv-step.