{"title":"Stress analysis and optimization of QFN solder joints under bending-torsion coupled conditions based on the SSA","authors":"Jisheng Wei, Chunyue Huang, Chao Gao, Gui Wang","doi":"10.1016/j.mejo.2025.106661","DOIUrl":null,"url":null,"abstract":"<div><div>A 3D finite element model of QFN (Quad Flat No-Lead Package) solder joints was established for stress–strain analysis under bending-torsion coupled loading. The accuracy of the finite element simulation was validated through bending-torsion coupled strain measurement experiments. The effects of pad length, pad width, solder joint standoff height, and PCB (Printed Circuit Board) thickness on bending-torsion coupled stress–strain behavior were analyzed using univariate and correlation analysis. To minimize stress, these parameters were optimized using the response surface-Sparrow Search Algorithm (SSA). Results show a weakly positive correlation for pad length, strong negative correlations for pad width and standoff height, and a strong positive correlation for PCB thickness. The optimal parameters – pad length 0.66 mm, pad width 0.25 mm, solder joint standoff height 0.09 mm, and PCB thickness 1.2 mm – reduced maximum stress by 10.8 MPa. The research findings provide theoretical guidance for reducing the bending-torsion coupled stress of QFN solder joints.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106661"},"PeriodicalIF":1.9000,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001109","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A 3D finite element model of QFN (Quad Flat No-Lead Package) solder joints was established for stress–strain analysis under bending-torsion coupled loading. The accuracy of the finite element simulation was validated through bending-torsion coupled strain measurement experiments. The effects of pad length, pad width, solder joint standoff height, and PCB (Printed Circuit Board) thickness on bending-torsion coupled stress–strain behavior were analyzed using univariate and correlation analysis. To minimize stress, these parameters were optimized using the response surface-Sparrow Search Algorithm (SSA). Results show a weakly positive correlation for pad length, strong negative correlations for pad width and standoff height, and a strong positive correlation for PCB thickness. The optimal parameters – pad length 0.66 mm, pad width 0.25 mm, solder joint standoff height 0.09 mm, and PCB thickness 1.2 mm – reduced maximum stress by 10.8 MPa. The research findings provide theoretical guidance for reducing the bending-torsion coupled stress of QFN solder joints.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.