Experimental investigations on the performance and bubble dynamics of two-phase immersion cooling system with multiple chips

Abstract

The continuous miniaturization of power electronics has led to increasingly compact devices, accompanied by a direct increase in the associated heat flux. Two-phase immersion cooling has established itself as a significant advancement for cooling high-power density systems; however, its performance in multi-chip configurations has not been extensively investigated. This study presents a fully experimental investigation to analyze the thermal performance and bubble dynamics in a two-phase immersion system with multiple chips. Experiments were conducted in an immersion tank with 10 mm thick aluminum walls, housing a printed circuit board with seven power resistor chips immersed in a dielectric liquid. The boiling process was recorded using a high-speed camera, and the images captured were analyzed to determine the bubble departure diameter (BDD) and bubble departure frequency (BDF). At a heat flux of 12.5 W/cm², the temperature of a specific chip increased by 15%, while the heat transfer coefficient (HTC) improved by 22.7% when all seven chips operated simultaneously, compared to when only that chip was powered. The BDD rose as heat flux increased while only the single chip was operating. However, when additional chips were activated, the BDD began to decrease beyond a critical Jakob number as the Jakob number increased with higher heat fluxes. At elevated Jakob numbers, the bulk liquid velocity increased, promoting the generation of a greater number of smaller bubbles instead of fewer, larger ones. The shrinking of bubbles and the enhancement of bulk liquid mixing contributed to the observed increase in the HTC as more chips were activated. A correlation for the average Nusselt number is developed as a function of the heat flux supplied to individual chips and the number of simultaneously operating chips. This correlation, expressed in terms of system control parameters, provides a framework for ensuring the thermal safety and reliable operation of multi-chip systems. The study concludes that under high computational workloads, distributing tasks across multiple processors is a more effective thermal management strategy compared to operating a single processor. This is largely because the activation of nearby chips enhances the HTC significantly due to reduced BDD and improved bulk liquid mixing.