{"title":"X-parameters modeling based on LSTM and CG-BPNN for transistor","authors":"Shu-yue Yang , Qian Lin , Hai-feng Wu","doi":"10.1016/j.mejo.2025.106646","DOIUrl":null,"url":null,"abstract":"<div><div>In order to reduce the time of device parameter measurement or simulation and improve the efficiency of circuit design, X-parameters of gallium nitride high electron mobility transistor (GaN HEMT) are modeled based on long short term memory (LSTM) and double hidden layer conjugate gradient back propagation neural network (CG-BPNN) in this paper. Then, to verify the modeling efficiency of the two models, the harmonic balance experiments are carried out to obtain the three harmonics of the predicted data and expected data. Finally, the three harmonic errors of LSTM model are 0.801, 7.511 and 13.470 dBm, respectively, and the three harmonic errors of double hidden layer CG-BPNN model are 0.1117, 2.594 and 3.423 dBm, respectively. Through the above experiments, it is proved that double hidden layer CG-BPNN model proposed here can effectively model GaN HEMT with large-signal. The application in engineering is the demonstration of superior performance of the proposed CG-BPNN model in terms of accurate representation of X-parameters for transistor.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106646"},"PeriodicalIF":1.9000,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125000955","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In order to reduce the time of device parameter measurement or simulation and improve the efficiency of circuit design, X-parameters of gallium nitride high electron mobility transistor (GaN HEMT) are modeled based on long short term memory (LSTM) and double hidden layer conjugate gradient back propagation neural network (CG-BPNN) in this paper. Then, to verify the modeling efficiency of the two models, the harmonic balance experiments are carried out to obtain the three harmonics of the predicted data and expected data. Finally, the three harmonic errors of LSTM model are 0.801, 7.511 and 13.470 dBm, respectively, and the three harmonic errors of double hidden layer CG-BPNN model are 0.1117, 2.594 and 3.423 dBm, respectively. Through the above experiments, it is proved that double hidden layer CG-BPNN model proposed here can effectively model GaN HEMT with large-signal. The application in engineering is the demonstration of superior performance of the proposed CG-BPNN model in terms of accurate representation of X-parameters for transistor.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.