An 8-bit 1.16 mw 500 ms/s SAR ADC with bidirectional-bit-distribution-based offset calibration and partially activated accelerating current source

Abstract

This paper presents an 8-bit 500MS/s single-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It features: 1) a fast-converging bidirectional-bit-distribution-based (BBDB) ping-pong comparator calibration, which bidirectionally adjusts the offset of the two comparators to their mean values, and reduces the offset standard deviation to 0.707 times initial offset value; and 2) the use of partially activated accelerating current source (ACS), depending on the operating state of the SAR ADC. When ACS is enabled, it reduces the single-bit decision time of the comparator by at least 14%. The prototype ADC, implemented in a 40 nm Low-Leakage CMOS process, achieves post simulated SNDR and SFDR of 47.4 dB and 65.7 dB, respectively, at Nyquist frequency input. Operating at a 1.1 V single supply, the ADC consumes 1.16 mW, leading to the Walden figure of merit (FoMw) of 12.2 fJ/conv-step.