A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain

Abstract

This paper presents a high-gain rail-to-rail operational amplifier architecture, characterized by its low voltage and high gain. The design incorporates a complementary PMOS and NMOS folded cascode, using a transconductance linear loop to bias the Class-AB stage for push–pull output. Furthermore, the circuit supports a wide input power supply voltage range, operating efficiently over an input voltage span of 1.8 V to 5 V. The op-amp was fabricated using a 90 nm BCD technology, with a core chip size of approximately $0.455\times 0.374{\text{mm}}^2$. Post-simulation results reveal a DC gain of 123 dB, a gain bandwidth of 0.86 MHz, and a noise level of $24\text{nV}/\sqrt{\text{Hz}}@10\text{kHz}$ with a 1.8 V supply voltage. Measurement outcomes demonstrate a slew rate of $0.157\text{V}/\mu \text{s}$ under loading conditions of 20pF and $10\text{k}\Omega$, with an output current of 1 mA and power consumption of $21.77\mu \text{A}$ and $25.26\mu \text{A}$ at 1.8 V and 5 V conditions, respectively.