Power Attack-Immune Spintronic-Based AES Hardware Accelerator for Secure and High-Performance PiM Architectures

Abstract

Concerns about data security have grown due to the increasing leakage power attributed to the scaling of CMOS technology. This necessitates the integration of spintronic devices, such as magnetic tunnel junctions (MTJs), with CMOS to mitigate leakage power and maintain data integrity. This article proposes a novel hybrid MTJ/CMOS architecture that implements the advanced encryption standard (AES) algorithm within a process-in-memory (PiM) framework to enhance data security. The key innovation is the architecture’s resilience to side-channel attacks, including differential power analysis (DPA) and correlation power analysis (CPA). Comprehensive post-layout simulations using the well-established 40-nm CMOS technology demonstrate that the power consumption patterns of each AES component remain constant, even under process variations. Furthermore, system-level simulations highlight that the proposed AES-128 architecture effectively resists information leakage and power attacks, even when exposed to numerous power traces used for key extraction. Comparative results indicate that our proposed power attack-resilient AES-128 hardware design outperforms existing application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) implementations, enhancing static power by 98% and boosting maximum frequency by 72% and 91%, respectively. The architecture’s adaptability for implementing other AES versions (AES-192 and AES-256) and substitution-based encryption algorithms further expands its versatility.