Novel approximate Booth multipliers (ABm-eRx) based on efficient encoding and reduction for error-tolerant applications

Abstract

Energy efficient and performance optimised multiplier hardware is of high demand as they are the fundamental and most significant block in every signal processing and computing unit. In addition, they are the most power-hunger blocks too. Thus, in this article, two novel and efficient Booth encoded multiplier architectures are proposed utilising approximate computing techniques. Efficient optimisation with good accuracy is achieved by using a combination of approximate encoding and approximate partial product reduction. The multiplier architectures ABm-eR1 and ABm-eR2 are implemented in Xilinx. Results reveal that the multipliers ABm-eR1, ABm-eR2 consume 9% and 10% lesser area in terms of LUTs along with noticeable power and delay reduction when compared to exact Booth encoded architecture. Simulations depict a minimal error of 1.31 × 10^–3 NMED which is on-par with existing approximate multipliers. In addition, the multipliers ABm-eR1 and ABm-eR2 when evaluated across image multiplication, sharpening and smoothing produced a PSNR of 42.27 db, 41.19 db, 40.26 db and 40.61 db, 39.32 db, 39.05 db respectively. These results demonstrate that the proposed multiplier architectures perform on-par with the existing approximate Booth multipliers when used for image processing applications. Intrinsic to their efficient performance, the proposed architectures are good candidates for realising error-resilient applications.