Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2025-02-06 DOI:10.1109/LCA.2025.3539282

Pooya Aghanoury;Santosh Ghosh;Nader Sehatbakhsh

引用次数: 0

Abstract

Hardware-assisted security features are a powerful tool for safeguarding computing systems against various attacks. However, integrating hardware security features (HWSFs) within complex System-on-Chip (SoC) architectures often leads to scalability issues and/or resource competition, impacting metrics such as area and power, ultimately leading to an undesirable trade-off between security and performance. In this study, we propose re-evaluating HWSF design constraints in light of the recent paradigm shift from integrated SoCs to chiplet-based architectures. Specifically, we explore the possibility of leveraging a centralized and versatile security module based on chiplets called security helper chiplets. We study the cost implications of using such a model by developing a new framework for cost analysis. Our analysis highlights the cost tradeoffs across different design strategies.

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安全辅助小芯片：安全硬件监控的新范例

硬件辅助安全特性是保护计算系统免受各种攻击的强大工具。然而，在复杂的片上系统（SoC）架构中集成硬件安全特性（hwsf）通常会导致可伸缩性问题和/或资源竞争，影响诸如面积和功耗等指标，最终导致安全性和性能之间的不良权衡。在这项研究中，我们建议根据最近从集成soc到基于芯片的架构的范式转变，重新评估HWSF的设计约束。具体来说，我们探讨了利用一种基于小芯片（称为安全助手小芯片）的集中和通用安全模块的可能性。我们通过开发一个新的成本分析框架来研究使用这种模型的成本含义。我们的分析强调了不同设计策略之间的成本权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.