Multi-chip Jet impingement cooling for heat dissipation in 2.5D integrated system with 1 kW+ thermal design power

Abstract

High-Performance computing (HPC) systems have multiple chips with dissimilar thermal dissipation and temperature constraints, integrated over a silicon interposer embedded with copper metal through silicon vias (TSVs), which makes its thermal management challenging. Temperature constraints of all chips are to be fulfilled simultaneously while also accounting for the complex thermal interactions among the chips through the interposer. This study experimentally and numerically investigates the performance of jet impingement cooling for a HPC system with a logic chip and four high bandwidth memory (HBM) chips, realized through copper blocks. The incoming fluid first impinges over the HBMs and is then redirected towards logic chip to impinge again, thus cooling the HBMs and Logic chip in series. The cooling strategy was able to achieve an unprecedented 1.86 kW of thermal design power subjected to maximum temperature constraint 105 °C and 85 °C for logic chip and HBMs, respectively. The minimum thermal resistance achieved was 0.183 cm².K/W while managing a logic chip heat flux as high as 252 W/cm². The corresponding pressure drop was a modest 48.32 kPa for a net chip area of 1060 mm². Surface temperature measurements at various locations over logic chip (676 mm²) reveal that surface temperature uniformity is within 3 °C even at the highest TDP. Comparison of series and parallel design, using numerical model, reveals the former's superior thermal performance and the ability to support HPCs with higher TDPs, subjected to the aforementioned temperature constraints.