A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection

Abstract

This paper proposes a dual-channel very short reach (VSR) SerDes transceiver designed for chip-to-chip (C2C) or chip-to-module (C2M) interconnections. The transmitter utilizes a half-rate architecture and is composed of high-speed multiplexers (MUXs), a clock distribution module, and an adjustable 3-tap feed-forward equalizer (FFE). The proposed receiver employs a half-rate oversampling architecture, consisting of a continuous time linear equalizer (CTLE), a CML-based static comparator, high-speed demultiplexers (DEMUXs), a multiphase clock generation module based on an active polyphase filter (APFF), a phase interpolator (PI), and a clock and data recovery (CDR) loop. This dual-channel transceiver is designed with a 28-nm CMOS process technology and supplied with 1/1.2 V. Post-simulation results show that this transceiver can operate at a data rate of 32 Gb/s with a power efficiency of 1.81 pJ/bit for transmitter and 3.5 pJ/bit for receiver. The transceiver’s BER is less than 1E-12 and eye-wide-opening is 0.86 UI, which is under 12.4 dB channel loss at 16 GHz Nyquist frequency.