G. Brindha , Preeti Narooka , M.K. Prathiba , Suhasini S. Goilkar
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引用次数: 0
Abstract
The growing popularity of paper-based digital microfluidic biochips (P-DMFBs) is attributed to their low cost and ease of fabricating electrodes and control circuits on a sheet of paper using inkjet printer and conductive ink. The complex design guidelines are employed for complete design viability, such as preventing induced control interference, reducing control line spacing, and guaranteeing congestion-free wiring in single layer. It takes careful consideration of cost-raising aspects, like wire length, schedule length, control pin count to achieve an effective fluid-control codesign. Therefore, Fluid-Control Codesign for Paper-dependent Digital Biochips using Volumetric Memory Networks: A Predictive Modelling Approach (FCC-DB-VMN) is proposed in this paper. This work offers a technique for pin-constrained P-DMFBs based on Volumetric Memory Networks that predict errors in control design and guides FCC to solve issues that drive costs while achieving congestion with conflict-free wiring. A low-cost platform is produced by this Volumetric Memory Networks (VMN) by eliminating design cycles. The proposed technique is evaluated using a balanced dataset. The proposed FCC-DB-VMN attains 20.67 %, 32.30 % and 18.52 % higher coefficient of accuracy, 15.03 %, 25.12 % and 25.64 % lower RMSE when compared with existing models: Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-dependent Digital Microfluidic Biochips (RL-DDQN-DMB), An integrated co-design of flow-dependent biochips considering flow-control design issues and objectives (ICD-FB-FCD), and Physical design for microfluidic biochips considering actual volume management along channel storage (PD-MFD-VMCS) respectively.
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.