Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding

Abstract

The ultrareliable low-latency communication (URLLC) application scenario requires the adoption of short linear block codes to satisfy the low-latency requirements. Guessing random additive noise decoding (GRAND) is a prominent universal decoding solution for short linear block codes that lends itself to efficient hardware implementations. GRAND-based hardware implementations generally offer reduced average decoding latency but their high worst-case (W.C.) latency renders them unsuitable for deployment in mission-critical applications. This article presents an improved version of step-GRAND, a soft-input variant of GRAND that features a novel test error pattern (TEP) generating approach. A novel very large-scale integration (VLSI) architecture is developed for the execution of the improved step-GRAND algorithm with reduced W.C. decoding latency. Application specific integrated circuit (ASIC) implementation results, employing low-power (LP) TSMC 65-nm CMOS technology, demonstrate that the proposed improved step-GRAND can achieve an average decoding latency as low as 10 ns for decoding a $(128,105)$ linear block code at a target frame error rate (FER) of $10^{-7}$ , while the W.C. decoding latency can reach $300~\text {ns}\sim 1~\mu \text { s}$ depending on the parametric settings. Compared with the previously proposed baseline soft-input ordered reliability bits GRAND (ORBGRAND) hardware implementation with similar decoding performance at target FER of $10^{-7}$ , the improved step-GRAND hardware achieves $7 \times \sim 17\times $ reduction in W.C. latency, $7\times $ reduction in power consumption, and $37 \times \sim 66\times $ higher area efficiency in the W.C. scenario. Furthermore, the proposed hardware can achieve an average throughput of up to 10.5 Gb/s and a W.C. throughput of $102\sim 350$ Mb/s.