High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200–237.5 TOPS/W

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-12-27 DOI:10.1109/TVLSI.2024.3519748

Wenjuan Lu;Lubin Xiang;Ling Wang;Chunyu Peng;Chenghu Dai;Zhiting Lin;Xiulong Wu

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引用次数: 0

Abstract

Artificial intelligence (AI) is extensively applied in natural language processing, image matching, and image recognition, with convolutional neural networks (CNNs) being crucial. Computing-in-memory (CIM) utilizing static random access memory (SRAM) can enhance the CNN performance. However, this faces issues such as multibit signed data processing, read corruption of traditional SRAM arrays, and increased area overhead due to increased capacitor weighting. This article proposes a 10T-SRAM macro tailored for CNN multiply-accumulate calculation (MAC) computation in image processing. It enables high-throughput full-array operations, with added dual ports facilitating input of multibit data with signed bits. The 10T-SRAM cell features a read-write separation channel, mitigating read disturbance issues seen in dual-port 8T-SRAM arrays or 6T-SRAM arrays. Incorporating redundant columns in the array for charge sharing and weighting conserves area and boosts circuit reliability. In the 28-nm CMOS simulation environment, the proposed architecture achieves a throughput of 274.3 GOPS and an energy efficiency of 200–237.5 TOPS/W, surpassing literature-reported figures by several times.

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高可靠性和高吞吐量的CIM 10T-SRAM，用于274.3 GOPS和200-237.5 TOPS/W的乘法和累加运算

人工智能（AI）广泛应用于自然语言处理、图像匹配和图像识别，其中卷积神经网络（cnn）至关重要。使用静态随机存取存储器（SRAM）的内存计算（CIM）可以提高CNN的性能。然而，这面临着诸如多位签名数据处理、传统SRAM阵列的读取损坏以及由于电容器权重增加而增加的面积开销等问题。本文提出了一种针对图像处理中CNN乘法累加计算（MAC）计算的10T-SRAM宏。它支持高吞吐量的全阵列操作，增加了双端口，方便输入带符号位的多比特数据。10T-SRAM单元具有读写分离通道，减轻了双端口8T-SRAM阵列或6T-SRAM阵列中出现的读取干扰问题。在阵列中合并冗余列以进行电荷共享和加权，节省了面积并提高了电路的可靠性。在28纳米CMOS仿真环境下，该架构实现了274.3 GOPS的吞吐量和200-237.5 TOPS/W的能效，比文献报道的数据高出几倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.