A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-11-19 DOI:10.1109/TVLSI.2024.3496669

Yuguo Xiang;Dayan Zhou;Minjia Song;Danfeng Zhai;Jingchao Lan;Junyan Ren;Fan Ye

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引用次数: 0

Abstract

This brief presents a digital calibration for pipelined analog-to-digital converters (ADCs) utilizing the cascaded nonlinearity correction (CNC) method. By cascading three correction layers for compensating nonlinearities in different parts of pipelined ADC, it comprehensively calibrates distortion in both ADC front end and back end with a low hardware cost. In addition, this work employs a discriminative fine-tuning least-mean-square (DFT-LMS) algorithm with varying step sizes for different layers, thereby improving both the convergence speed and the accuracy. An 800-MS/s, 12-bit ring amplifier-based pipelined ADC is presented to verify the proposed calibration technique. With calibration, the SFDR has a 26.7-dB improvement at low frequency and 23.6-dB improvement at Nyquist frequency, resulting in over 6-dB improvement compared with prior-art calibration techniques. The calibration algorithm has been verified on a TSMC 28-nm CMOS process. The experimental results show that the proposed ADC calibrator has an area of

$6592~\mu $

m2 and consumes 5.31 mW at 800-MHz clock rate.

查看原文本刊更多论文

本简介介绍了一种利用级联非线性校正（CNC）方法对流水线模数转换器（ADC）进行数字校正的方法。通过级联三个校正层来补偿流水线模数转换器不同部分的非线性，它能以较低的硬件成本全面校正模数转换器前端和后端的失真。此外，这项工作还采用了一种判别微调最小均方（DFT-LMS）算法，不同层的步长各不相同，从而提高了收敛速度和精度。为了验证所提出的校准技术，本文介绍了一种基于环形放大器的 800-MS/s 12 位流水线 ADC。通过校准，SFDR 在低频时提高了 26.7 分贝，在奈奎斯特频率时提高了 23.6 分贝，与之前的校准技术相比提高了 6 分贝以上。该校准算法已在台积电 28 纳米 CMOS 工艺上得到验证。实验结果表明，所提出的 ADC 校准器的面积为 6592~mu $ m2，在 800-MHz 时钟频率下的功耗为 5.31 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.