A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique

Abstract

This article presents a low-jitter sub-sampling chopper phase-locked loop (SS-CPLL) that incorporates a novel chopping charge pump (C-CP) to mitigate 1/f noise in short-channel devices operating at a low supply voltage of 0.75 V. A charge-share cancellation technique is introduced to suppress ripple generated by residual charge from the previous reference period. The chopping modulation further reduces the charge pump’s white noise by filtering out high-order harmonics of folded noise, thereby significantly lowering in-band noise. In addition, a high-swing class-C/F2 voltage-controlled oscillator (VCO) is proposed to optimize out-of-band noise while maintaining low power consumption. Fabricated in 65-nm complementary metal oxide semiconductor (CMOS) with a core area of 0.64 mm2, the SS-CPLL achieves an in-band phase noise of −111.9 dBc/Hz at 1-kHz offset, an integrated jitter of 49.9 fs, and a figure-of-merit (FoM) of −257.1 dB at 9 GHz, while consuming 7.8 mW of power. The proposed SS-CPLL reduces in-band noise by approximately 15 dB compared with a conventional sub-sampling phase-locked loop (SSPLL), while maintaining a similar reference spur level of −58 dBc/Hz. This highlights the effectiveness of the C-CP and charge-share cancellation techniques.