An ultra-fast settling and low area bit synchronizer architecture

Abstract

The paper presents the architecture design of a bit synchronizer suited for wireless sensor node applications. It detects a 0–1 transition sent from transmitter that subsequently triggers a counter clocked by a reference. The counter counts a certain number of reference cycles and generates a strobe signal that is used to sample the demodulated waveform at the maximum signal to noise ratio (SNR) instant. Because of the position of the maximum SNR point, there is a latency in the strobe signal. This latency can be measured off-chip and on-chip. Off-chip solution entails observing a repetitive 0–1 pattern sent from the transmitter, and the reference clock post fabrication in an oscilloscope in test lab and writing the latency in terms of reference cycle counts into the chip. On-chip solution uses samplers to sample the demodulated waveform at multiple instants and finds the time where the maximum sampled value occurs. Algorithm was designed first from which the architecture was generated. For the off-chip method, circuit design followed by layout was also performed. The bit synchronizer requires just two bits (for on-chip solution three bits are required) to align with the optimum sampling instant which is very fast compared to existing literature and hence has ultra-fast settling capability. The circuit requires 2364 transistors and the area occupied is 0.069mm². Power consumption is also low being 7.26 µW while bit error ratio less than 10⁻³ was achieved for different parameter settings. The receiver design has been targeted for implant telemetry in the 402-405 MHz frequency band.