Interfacial delamination on fan-out wafer-level package using finite element analysis

Abstract

Fan-out wafer-level packaging has become a widely known approach for achieving a microelectronic device with low cost, smaller package size, and good electrical performance. Large temperature variations occur during these fabrication processes which can induce internal stresses and interfacial delamination due to the large thermal expansion mismatch. In this study, a finite element method was performed to study the potential interfacial delamination on the fan-out wafer-level package. The maximum warpage of the wafer right after the post-mold curing was found to be 619.4 µm. It was predicted that the maximum normal and shear stresses of 45.96 MPa and 88.34 MPa, respectively, at one corner of the EMC-chip interface exceeded its adhesion strength. The virtual crack closure technique was used to evaluate the delamination in terms of total energy release rate on the interface of the individual package of fan-out wafer-level packaging when subjected to a high-temperature solder reflow process. A global-to-local modeling of the individual package was also employed in the study. The results of the designs of experiment have shown that the most influential factor in interfacial delamination was the value of the coefficient of thermal expansion of the epoxy molding compound above its glass transition temperature. It was found that increasing this coefficient while maintaining other material properties and parameters would also increase the energy release rate and would even exceed the critical value of 0.2 mJ/mm² at the interface of the Silicon chip and epoxy molding compound. The safe maximum value of the coefficient of thermal expansion of the epoxy molding compound was found to be 42.56 ppm/ °C.