Enhanced platform-based interrupt controller for RISC-V MCUs

Abstract

Interrupt efficiency including latency is a critical factor in the performance of real-time embedded microcontroller units (MCUs) used for the internet of things (IoT). RISC-V MCUs often suffer from greater interrupt latency due to the extensive software intervention required by the conventional Platform-Level Interrupt Controller (PLIC), in contrast to ARM Cortex-M MCUs that employ hardware-accelerated, vectored interrupt handling. Although the Core Local Interrupt Controller (CLIC) has mitigated some latency issues, its lack of native support in many open-source RISC-V cores restricts its widespread adoption. This work introduces an Enhanced PLIC (EPLIC) that incorporates hardware-accelerated features such as vectored scheduling, context saving and restoration, interrupt nesting, and tail-chaining to optimize the Interrupt Service Routine (ISR). Implemented in the open-source Ibex core, EPLIC not only substantially reduces interrupt latency to 7 clock cycles but also achieves interrupt performance on par with commercial MCUs based on ARM’s Cortex-M processors. This work had been implemented in a smart electricity meter System-on-Chip (SoC).