A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization

Abstract

The Ising model has shown outstanding potential for solving combinatorial optimization problems, but conventional processors based on the von Neumann architecture have difficulty emulating the behavior of spins in parallel. Therefore, to tackle combinatorial optimization problems efficiently, specialized processors with Ising models are required. In this work, an approximate logistic complementary spin update (ALCU) model is proposed that enhances the accuracy of the solution by 3.34% compared to the previous approximation methodology. In addition, an adaptive analog majority voter (AMV) is proposed, which can support higher interaction coefficient bit-width and more interaction spins with lower hardware overhead. Then, the Ising machine with 100 interaction spins in King’s Graph topology is implemented based on a 28 nm CMOS process. More than 67% less hardware overhead is required when compared to Ising machines based on digital adders. The coefficient precision is increased to 2.3x, and the number of interaction spins is increased to 1.6x compared to the Ising machine based on prior AMV.