A Technique for Optimal On-Wafer Device Spacing at Millimeter-Wave Frequencies

Abstract

In this letter, we present a technique to determine efficient placement of nearby structures to the device-under-test (DUT) based on the DUT’s impedance, which is overlooked in the current layout guidelines. This technique involves sweeping both the impedance of the DUT and the spatial location of the nearby structure to create a map where the structure can be placed that would simultaneously minimize coupling to the DUT as well as the space between devices. The simulations were validated up to 110 GHz using gallium nitride (GaN) high-electron-mobility transistor (HEMT) measurements with and without a nearby line.